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Genesys Logic, Inc.
GL9701
PCI ExpressTM to PCI Bridge
Datasheet Revision 0.90 Sep. 05, 2006
GL9701 PCI ExpressTM to PCI Bridge
Copyright:
Copyright (c) 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc..
Disclaimer:
ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com
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GL9701 PCI ExpressTM to PCI Bridge
Revision History
Revision 0.90 Date 2006/09/05 First formal release Description
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GL9701 PCI ExpressTM to PCI Bridge
TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION.................................................... 9 CHAPTER 2 FEATURES ............................................................................ 10 2.1 PCI EXPRESS FEATURES........................................................................ 10 2.2 PCI INTERFACE FEATURES ................................................................... 10 2.3 POWER MANAGEMENT .......................................................................... 10 2.4 SMBUS INTERFACE ............................................................................... 11 CHAPTER 3 PIN ASSIGNMENT ............................................................... 12 3.1 PIN CONFIGURATION ............................................................................. 12 3.2 PINOUT.................................................................................................. 13 3.3NUMERIC PIN ASSIGNMENT LIST ........................................................... 14 3.4 SIGNAL DESCRIPTION ............................................................................ 16 3.4.1 PCI-Express Interface.................................................................. 16 3.4.2 Secondary PCI Interface.............................................................. 17 3.4.3 EEPROM Signals ......................................................................... 18 3.4.4 Miscellaneous Signals ................................................................... 18 3.4.5 Power and Ground Signals .......................................................... 19 CHAPTER 4 BLOCK DIAGRAM............................................................... 21 CHAPTER 5 FUNCTION DESCRIPTION ................................................ 24 5.1 POWER MANAGEMENT .......................................................................... 24 5.1.1 PCI-PM Software Compatible Power Management .................. 24 5.1.2 Hardware-Controlled Active State Power Management............ 24 5.1.3 In-band Beacon............................................................................. 24 5.1.4 Side-band WAKE_N .................................................................... 25 5.1.5 Power Management System Messages ........................................ 25 5.2 PCI CLOCK RUN.................................................................................... 25 5.3 PCI CLOCK............................................................................................ 25 5.4 INTERRUPT MAPPING ............................................................................. 26 5.5 INITIAL FLOW CONTROL ADVERTISEMENTS ......................................... 27 5.6 IDSEL MAPPING ................................................................................... 28 CHAPTER 6 REGISTER DESCRIPTION ................................................. 29 6.1 OFFSET 00H: DEVICE IDENTIFICATION.................................................. 34 6.2 OFFSET 04H: COMMAND REGISTER ...................................................... 34 6.3 OFFSET 06H: STATUS REGISTER............................................................ 35
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GL9701 PCI ExpressTM to PCI Bridge
6.4 OFFSET 08H: REVISION ID .................................................................... 37 6.5 OFFSET 09H: CLASS CODE..................................................................... 37 6.6 OFFSET 0CH: CACHE LINE SIZE REGISTER ........................................... 38 6.7 OFFSET 0DH: PRIMARY LATENCY TIMER REGISTER............................. 38 6.8 OFFSET 0EH: HEADER TYPE REGISTER................................................. 38 6.9 OFFSET 0FH: BIST REGISTER................................................................. 38 6.10 OFFSET 10H: BASE REGISTER0............................................................ 38 6.11 OFFSET 14H: BASE REGISTER1............................................................ 38 6.12 OFFSET 18H: PRIMARY BUS NUMBER REGISTER................................. 39 6.13 OFFSET 19H: SECONDARY BUS NUMBER REGISTER ............................ 39 6.14 OFFSET 1AH: SUBORDINATE BUS NUMBER REGISTER......................... 39 6.15 OFFSET 1BH: SECONDARY LATENCY TIMER REGISTER ...................... 39 6.16 OFFSET 1CH: IO BASE AND IO LIMIT REGISTER................................. 39 6.17 OFFSET 1EH: SECONDARY STATUS REGISTER ..................................... 40 6.18 OFFSET 20H: MEMORY BASE AND LIMIT REGISTER ........................... 42 6.19 OFFSET 24H: PREFETCHABLE MEMORY BASE AND LIMIT REGISTER . 42 6.20 OFFSET 28H: PREFETCHABLE BASE UPPER 32-BITS REGISTER........... 43 6.21 OFFSET 2CH: PREFETCHABLE LIMIT UPPER 32-BITS REGISTER ......... 43 6.22 OFFSET 30H: IO BASE AND LIMIT UPPER 16-BITS REGISTER.............. 43 6.23 OFFSET 34H: CAPABILITIES POINTER REGISTER ................................ 43 6.24 OFFSET 3CH: INTERRUPT LINE REGISTER........................................... 44 6.25 OFFSET 3DH: INTERRUPT PIN REGISTER ............................................. 44 6.26 OFFSET 3EH: BRIDGE CONTROL REGISTER......................................... 44 6.27 OFFSET 70H: PCI EXPRESS CAPABILITY LIST REGISTER.................... 48 6.28 OFFSET 72H: PCI EXPRESS CAPABILITIES REGISTER ......................... 48 6.29 OFFSET 74H: PCI EXPRESS DEVICE CAPABILITIES REGISTER............ 49 6.30 OFFSET 78H: PCI EXPRESS DEVICE CONTROL REGISTER .................. 49 6.31 OFFSET 7AH: PCI EXPRESS DEVICE STATUS REGISTER...................... 50 6.32 OFFSET 7CH: PCI EXPRESS LINK CAPABILITIES REGISTER................ 51 6.33 OFFSET 80H: PCI EXPRESS LINK CONTROL REGISTER ...................... 52 6.34 OFFSET 82H: PCI EXPRESS LINK STATUS REGISTER .......................... 52 6.35 OFFSET 94H: PM CAPABILITY ID REGISTER ...................................... 53 6.36 OFFSET 95H: PM NEXT POINTER REGISTER ....................................... 53 6.37 OFFSET 96H: POWER MANAGEMENT CAPABILITIES REGISTER .......... 53
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6.38 OFFSET 98H: POWER MANAGEMENT CONTROL AND STATUS REGISTER .................................................................................................... 54 6.39 OFFSET A0H: SLOT NUMBERING CAPABILITIES ID REGISTER ............ 54 6.40 OFFSET A1H: SLOT NUMBERING POINTER TO NEXT ID REGISTER ..... 55 6.41 OFFSET A2H: SLOT NUMBERING EXPANSION SLOT REGISTER............ 55 6.42 OFFSET A3H: SLOT NUMBERING CHASSIS NUMBER REGISTER ........... 55 6.43 OFFSET 100H: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER REGISTER ................................................................. 55 6.44 OFFSET 104H: UNCORRECTABLE ERROR STATUS REGISTER .............. 56 6.45 OFFSET 108H: UNCORRECTABLE ERROR MASK REGISTER ................ 56 6.46 OFFSET 10CH: UNCORRECTABLE ERROR SEVERITY REGISTER .......... 57 6.47 OFFSET 110H: CORRECTABLE ERROR STATUS REGISTER................... 57 6.48 OFFSET 114H: CORRECTABLE ERROR MASK REGISTER..................... 57 6.49 OFFSET 118H: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER .................................................................................................... 58 6.50 OFFSET 11CH: HEADER LOG REGISTER .............................................. 58 6.51 OFFSET 12CH: SECONDARY UNCORRECTABLE ERROR STATUS REGISTER .................................................................................................... 58 6.52 OFFSET 130H: SECONDARY UNCORRECTABLE ERROR MASK REGISTER .................................................................................................... 59 6.53 OFFSET 134H: SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER .................................................................................................... 60 6.54 OFFSET 138H: SECONDARY ERROR CAPABILITIES AND CONTROL REGISTER .................................................................................................... 60 6.55 OFFSET 13CH: SECONDARY HEADER LOG REGISTER ......................... 61 6.56 OFFSET 150H: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER REGISTER...................................................................................... 61 6.57 OFFSET 154H: DEVICE SERIAL NUMBER REGISTER ............................ 61 CHAPTER 7 ELECTRICAL CHARACTERISTICS ................................ 62 7.1 OPERATION CONDITIONS....................................................................... 62 7.3 DIFFERENTIAL RECEIVER (RX) INPUT SPECIFICATION......................... 68 7.4 PCI INTERFACE DC SPECIFICATIONS ................................................... 70 7.5 PCI INTERFACE AC SPECIFICATIONS ................................................... 71 7.6 CLOCK AND RESET SPECIFICATIONS ..................................................... 72 CHAPTER 8 PACKAGE DIMENSION...................................................... 74
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 9 ORDERING INFORMATION.............................................. 75
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GL9701 PCI ExpressTM to PCI Bridge
LIST OF FIGURES
FIGURE 3.1PIN CONFIGURATION ................................................................................12 FIGURE 3.2PIN OUT DIAGRAM ....................................................................................13 FIGURE 4.1GL9701 BLOCK DIAGRAM .........................................................................21 FIGURE 6.1GL9701 CAPABILITIES..............................................................................31 FIGURE 8.1GL9701 128 PIN LQFP PACKAGE ............................................................74
LIST OF TABLES
TABLE 3.1SIGNAL TYPE..............................................................................................14 TABLE 4.1SUPPORTED PCI COMMAND.......................................................................22 TABLE 6.1NOTATION FOR ATTRIBUTE ........................................................................30 TABLE 6.2LEGACY CONFIGURATION SPACE...............................................................33 TABLE 6.3PCI EXPRESS EXTENDED CONFIGURATION SPACE.....................................33 TABLE 9.1ORDERING INFORMATION ..........................................................................75
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 1 GENERAL DESCRIPTION
PCI Express is a general-purpose interconnection technology to achieve high performance and flexibility at competitive cost for future computing and communication platforms. The GL9701 PCI Express to PCI Bridge provides a solution to connect PCI Express with existing PCI domain. This is referred to as a "PCI Express to PCI bridge" or simply as a "bridge", which features a PCI Express primary interface and a PCI secondary interface. A bridge can be used to enable existing PCI based application to plug into a PCI Express based system.
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 2 FEATURES
2.1 PCI Express Features
* * * * * * * * * * * Compliant to PCI Express Base Specification Revision 1.0a Compliant to PCI Express to PCI Bridge Specification Revision 1.0 Support Single One-Lane PCI Express Connection Support 32-bit CRC Covering All Transmitted Data Packets Support 16-bit CRC On All Link Message Information Support PCI Express Advanced Error Reporting Capability Support Error Forwarding Including Data Poisoning and PCI Bus Parity Errors. Support 100MHz PCI Express Differential Reference Clock. Secondary Side Initialization via Type 0 Configuration Cycles Support Variable Payload Size (up to 512 bytes) Support Variable Size of Read Request (up to 512 bytes)
2.2 PCI Interface Features *
* * * * * * Compliant to PCI Local Bus Specification Revision 3.0 Support PCI 32-bit, 33/66 MHz, 3.3V, NOT 5V tolerant Support Five External REQ/GNT Pairs For Internal Arbiter Support PCI LOCK Operation Support up to Two PCI Delayed Transaction (memory read, I/O read/write, and configuration read/write) Support Clock Run Operation Support Five 33MHz/66MHz PCI Clock Outputs
2.3 Power Management
* * * * * * * Support D0, D1, D2, D3hot and D3cold device power states defined in PCI Power Management Specification Rev 1.1 Support PME event propagation on behalf of PCI devices Side-band WAKE# signals PCI Express Active Power Management states (ASPM) : L0s and L1 Support link power management: L0, L0s, L1, L2 In-band beacon generation Integrated AUX Power Plane
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GL9701 PCI ExpressTM to PCI Bridge 2.4 SMBus Interface
* * * Compliant to System Management Bus Specification, Revision 2.0 Support Slave-mode operation only Support configuration of PCI Express PHY via SMBus
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 3 Pin Assignment
The "_N" symbol at the end of signal name indicates that the active (asserted) state occurs when the signal is at low voltage level. When "_N" is not present after the signal name, the signal is asserted at the high voltage level.
3.1 Pin Configuration
Figure 3.1Pin Configuration
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GL9701 PCI ExpressTM to PCI Bridge 3.2 PinOut
GL9701 uses LQFP128 package. Figure 4.2 presents the Pin out Diagram of GL9701.
Figure 3.2Pin out Diagram
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GL9701 PCI ExpressTM to PCI Bridge
The following notations are used to describe signal type:
Signal Type I O TS STS Input pin. Output pin Tri-state input/output pin.
Description
Sustained Tri-State is an active low tri-state Signal owned and driven by one and only one agent at a time.
P OD LVDO LVDI
Power pin Open Drain allows multiple devices to share as a wire-OR. Low-voltage differential output Low-voltage differential input
Table 3.1Signal Type
3.3Numeric Pin Assignment List
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name VSS33 VDD33 AD26 AD25 AD24 CBE3_N AD23 AD22 AD21 AD20 VSS33 VDD33 P P TS TS TS TS TS TS TS TS P P Type Pin Number 65 66 67 68 69 70 71 72 73 74 75 76 Pin Name GPIO6 REQ2_N GNT2_N CLKRUN_N CLKRUN_N_EN VSS18_AUX VDD18_AUX VSSGR REFCLKP REFCLKN VDDPLL VSSPLL TS I O I TS P P P LVDI LVDI P P Type
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GL9701 PCI ExpressTM to PCI Bridge
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
AD19 AD18 AD17 AD16 CBE2_N FRAME_N VSS18 VDD18 IRDY_N TRDY_N VSS33 VDD33 DEVSEL_N STOP_N LOCK_N PER_N SER_N PAR CBE1_N AD15 VSS33 VDD33 AD14 AD13 AD12 AD11 AD10 M66EN AD9 AD8 VSS33 VDD33 CBE0_N
TS TS TS TS TS STS P P STS TS P P STS STS STS TS OD TS TS TS P P TS TS TS TS TS I TS TS P P TS
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
RTERM VSSRX RXP RXN VDDRX VSS18_AUX VDD18_AUX VSSTX TXP TXN VDDTX AVSSPCI AVDDPCI TESTD TESTC WAKE_N VSS33_AUX VDD33_AUX PERST_N PME_N VDD18_AUX VSS18_AUX OPMODE1 OPMODE0 REQ3_N GPIO3 GPIO4 VSS33 VDD33 INTA_N GNT4_N REQ4_N GPIO5
I P LVDI LVDI P P P P LVDO LVDO P P P TS I DO P P I I P P I I I TS TS P P TS O I TS
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GL9701 PCI ExpressTM to PCI Bridge
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
AD7 AD6 AD5 AD4 AD3 VSS18 VDD18 AD2 AD1 AD0 VSS33 VDD33 GPIO0 GPIO1 GPIO2 PROMCS PROMDO PROMDI PROMSK
TS TS TS TS TS P P TS TS TS P P TS TS TS O O I O
110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
PCICLKI INTB_N INTC_N INTD_N GNT3_N GNT1_N PCIRST_N VSS18 VDD18 VSS33 VDD33 REQ1_N GNT0_N REQ0_N AD31 AD30 AD29 AD28 AD27
I I I I O O O P P P P I O I TS TS TS TS TS
3.4 Signal Description 3.4.1 PCI-Express Interface
Name TXP, TXN RXP, RXN REFCLKP, REFCLKN PERST_N RTERM I I External reset, low active Connect to a resistor for calibration LVDI 100 MHz differential clock input LVDI Receiver differential pair Type LVDO Transmitter differential pair Description
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GL9701 PCI ExpressTM to PCI Bridge 3.4.2 Secondary PCI Interface
Name AD[31:0] CBE[3:0]_N FRAME_N IRDY_N TRDY_N STOP_N DEVSEL_N PAR PER_N SER_N PCIRST_N LOCK_N REQ[4:0]_N Type TS TS STS STS STS STS STS TS STS OD O STS I Address/Data Command/Byte Enable Secondary PCI interface frame Secondary PCI interface initiator ready Secondary PCI interface target ready Secondary PCI interface stop indicator Secondary PCI interface device select Secondary PCI interface parity Secondary PCI interface parity error detect Secondary PCI interface system error Secondary PCI bus Reset Secondary PCI interface target ready Requests 4-0, activated by the secondary bus masters to request the use of the secondary bus. REQ0_N is a dual-purpose signal. When the bridge's internal arbiter is enabled, this signal is used as a request input, to be activated by a secondary bus master requesting the use of the secondary bus. When the internal arbiter is disabled, REQ0_N is used by the bridge as its grant input signal. GNT[4:0]_N O Grants 4-0, activated by the bridge's internal arbiter to grant usage of the secondary bus to the master that activated the corresponding request signal. GNT0_N is a dual-purpose signal. When the bridge's internal arbiter is enabled, this signal is used as a grant output, activated by the bridge to grant the use of the secondary bus to the master who requested the use with the GNT0_N signal. When the internal arbiter is disabled, this signal is used by the bridge as its request output signal. PCICLKI INTA_N, INTB_N, INTC_N, I I PCI clock input. Interrupt from secondary interface. Description
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GL9701 PCI ExpressTM to PCI Bridge
INTD_N PME_N WAKE_N I OD Power management event from secondary interface Used to implement wakeup mechanism.
3.4.3 EEPROM Signals
Name PROMCS PROMDO PROMDI PROMSK Type O O I O Enable EEPROM interface Serial data output for EEPROM Serial data input from EEPROM Serial clock output for EEPROM Description
3.4.4 Miscellaneous Signals
Name GPIO[6:0] Type TS Description The output signals are determined by OPMODE[1:0], PCICLKx_MASK(x=0~5) in design option. For GPIO[2:0]: Available only in normal mode. (OPMODE[1:0]=2'b00) If PCICLKx_MASK (x=0~2) are not masked (=1'b0), then these three bits are used as PCI clock outputs. It's recommended that GPIO[0] be routed to PCICLKI input. If PCICLKx_MASK (x=0~2) are masked (=1'b1) then these three bits are used as output of GPIO signal from design option. For GPIO[5:3]: If in normal function mode (OPMODE[1:0]=2'b00), then these three bits are used as PCI clock outputs when PCICLKx_MASK(x=5~3) are not masked (=1'b0). These three bits are used as GPIO output from design option if PCICLKx_MASK(x=5~3) are masked (=1'b1). If in test mode (OPMODE[1:0]=2'b01), then these three bits are used as internal signal output. For GPIO[6]: If in normal function mode (OPMODE[1:0]=2'b00), the bit is used as GPIO pins. Users can specify the output value and
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GL9701 PCI ExpressTM to PCI Bridge
output enable via design option. Users can also probe the input value by reading the design option. If in normal function (OPMODE[1:0]=2'b01), then this bit is used as internal signal output. OPMODE[1:0] TESTC TESTD CLKRUN_N I I TS TS Operation mode setup Test clock Test data A PCI device can request GL9701 to start, speed up, or maintain the PCI clock by the assertion of CLKRUN_N. GL9701 is responsible for maintaining CLKRUN_N asserted, and for driving it high to the de-asserted state. CLKRUN_N_E N I Clock Run Enable 1'b1: Enable Clock Run 1'b0: Disable Clock Run M66EN I Enable PCI clock act as 33MHz or 66MHz. 1: PCI Clocks are 66MHz. 0: PCI clocks are 33MHz
3.4.5 Power and Ground Signals
Name VSS33 VDD33 VSS18_AUX VDD18_AUX VSS33_AUX VDD33_AUX VSS18 VDD18 VSSGR VDDPLL VSSPLL VSSRX VDDRX Type P P P P P P P P P P P P Ground for PCI PAD 3.3V Power Supplier for PCI PAD Ground for 1.8 Vaux 1.8Vaux Power Supplies for core voltage Ground for 3.3 Vaux 3.3Vaux Power Supplies for core voltage Digital ground 1.8V Power Supplies for core voltage Ground for the guard ring of the SerDes block 1.8V Power Supplies for internal PLL Ground for internal PLL 1.8V Power Supplies for receiver part Description
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GL9701 PCI ExpressTM to PCI Bridge
VSSTX VDDTX AVSSPCI AVDDPCI
P
1.8V Power Supplies for transceiver part
P
1.8V Power Supplier for PCI PLL
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 4 Block Diagram
PCI Interface EEPROM Interface
PCI
Bus Arbiter
EEC
Transaction Translator
Configuration Registers
PCI Express Transaction Layer
PCI Express Data Link Layer
Power Management
PCI Express MAC Layer
Clocking/ Reset
Ref. Clock
PCI Express x1 PHY
SMBus Slave
PCI Express Link
SMBus Signals
Figure 4.1GL9701 block diagram
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GL9701 PCI ExpressTM to PCI Bridge
The GL9701 is composed of the following major functional blocks as shown in Figure 3-1: * PCI interface macro The macro acts as either a bus master or a bus slave and handles the PCI protocol depending on the transaction types. GL9701 supports 32-bit PCI addressing with 0MHz~33MHz and 66MHz operation frequency. Table3.1 summarizes the PCI commands supported by GL9701
Command Type I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write and Invalidate
Encoding 0010 0011 0110 0111 1010 1011 1100 1110 1111
Table 4.1Supported PCI Command
*
Bus Arbiter This block supports PCI bus arbiter for secondary PCI bus. The bus arbitration is provided by GL9701 and supports up to five external masters. The arbiter can be disabled by external EEPROM.
*
Configuration Registers This module supports two mechanisms for configuration space access: PCI compatible and PCI Express enhanced configuration mechanism.
*
Power Management The moudle is in charge of power management event signaling. This module enables GL9701 to enter software driven D-state transitions.
*
Transaction Translator The Transaction Translator manages all the bridge operation between PCI Express and PCI interface. It is responsible for PCI Express to PCI command translation, message translation and managing transaction ordering.
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GL9701 PCI ExpressTM to PCI Bridge
* PCI Express Transaction Layer The layer's function is the assembly and disassembly of Transaction Layer Packets (TLPs). It is also responsible for managing credit-based flow control for TLPs. * PCI Express Data Link Layer The layer serves as an intermediate stage between the Transaction Layer and the Physical Layer. The responsibility is Link management and data integrity including error detection and error correction. * PCI Express MAC Layer The Layer can be taken as a part of Physical Layer. It includes link initialization, link state management, lane alignment, data scrambling and descrambling. * PCI Express x1 PHY The PHY includes all circuitry for interface operation for an x1 link, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s) and impedance matching circuitry. It also includes logical function related to 8b/10b encoding/decoding and PHY status report. * SMBus Slave The SMBus Slave handles SMBus protocol and provides the access to internal registers such as chip information, function options and some test setting. * * EEC, EERPOM Controller Provide a download path for chip configuration and information. Clocking/Reset Provide a clocking and reset to manage all blocks.
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 5 Function Description
5.1 Power Management
GL9701 supports PCI-PM 1.1 Compatible Power Management and Active State Power Management (ASPM) defined in PCI Express Base Specification Revision 1.0a.
5.1.1 PCI-PM Software Compatible Power Management
GL9701 supports link states L0, L1 and L2 needed to implement PCI-PM compatible power states D0, D1, D2 and D3hot. All link states are determined by the D-state of the bridge. Because GL9711 provides Vaux, bridge will enter into L2 state when software direct bridge into D3hot state. Refer to the PCI Express Base Specification Revision 1.0a for more protocol information involved in transitioning the link to the L1 or L2 state.
5.1.2 Hardware-Controlled Active State Power Management
GL9701 supports a hardware-initiated power management mechanism which is called Active State Power Management (ASPM). Once this feature is enabled, bridge will drive the link state into a low-power L0s link state or even lower-power L1 link state. Refer to the PCI Express Base Specification Revision 1.0a for more information about ASPM.
Once system software enables GL9701's ASPM capability by setting the ASPM Control bit of Link Control Register to high, GL9701 will behavior ASPM specified in PCI Express Base Specification Revision 1.0a by default. However, GL9701 can disable this mechanism via the optional setting specified in table6.1. The optional bit is the 30th bit of Configuration Space Register with offset `hc8. If this bit is set to low, then GL9701 will never act ASPM behavior no matter what value of the ASPM Control bit of Link Control Register.
5.1.3 In-band Beacon
Beacon is a in-band signal used to exit the L2 link power management state and informs the Root Complex to re-activate the link. When the bridge is directed into D3hot State, the link state will finally stay in L2 State. The device on the secondary PCI bus wakes up the system by asserting PME_N. GL9701 then outputs the beacon signal on the upstream PCI Express link. Root complex should re-apply the power and reference clock again after detecting the beacon.
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GL9701 PCI ExpressTM to PCI Bridge 5.1.4 Side-band WAKE_N
GL9701 supports two means to signal the platform to re-establish the power and reference clock while the bridge is placed into D3hot state. One is Beacon, and the other is WAKE_N. WAKE_N.
WAKE_N is a side-band signal and is low active. Similar with Beacon, the bridge only outputs WAKE_N when the bridge detects PME_N asserted by the device on the secondary PCI bus when the bridge is placed into D3hot state.
5.1.5 Power Management System Messages
GL9701 supports all messages involved in the Power Management. GL9701 either initiates or receives them. Table5-1 outlines their characteristics. Packet PM_Enter_L1 PM_Enter_L23 PM_Active_State_Request_L1 PM_Request_Ack PM_Active_State_Nak PM_PME PME_Turn_Off PME_TO_Ack Type DLLP DLLP DLLP DLLP TLP TLP TLP TLP
5.2 PCI Clock Run
GL9701 supports Clock Run functionality specified in PCI Mobile Design Guide v1.1. CLKRUN_N is an optional signal used by devices to request starting (or speeding up) the clock. A device requests the central resource to start, speed up, or maintain the PCI clock by the assertion of CLKRUN_N. The central resource is responsible for maintaining CLKRUN_N asserted, and for driving it high to the de-asserted state.
Clock Run functionality in GL9701 can be enabled by the asserting CLKRUN_N_EN (PIN69) to high. When the function is enabled, GL9701 plays the role of central resource. There is a ODT inside the CLKRUN_N (PIN68), so there is no need to add an external pull up resistor on the CLKRUN_N.
5.3 PCI Clock
GL9701 supports five PCI slots on the secondary PCI interface. To provide the devices on these slots and GL9701 itself can work properly, GL9701 provides six PCI clock sources.
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GL9701 PCI ExpressTM to PCI Bridge
The operational frequency of these PCI clocks can be configured by M66EN (PIN40). When it's set to high, then the PCI clocks will operate at 66MHz. When it's set to low, then these clocks will operate at 33MHz.
The six clock output are at GLIO0 ~ GPIO5. It's recommended that GPIO0 be connected to PCICLKI (PIN110) to feed GL9701 itself. GPIO1 ~ GPIO5 then can be distributed to the five PCI slots. Users may optionally implement the number of PCI slots greater than one and less than five. Users can even use an external PCI clock source to maintain the normal operation of GL9701 and its secondary PCI slots.
If not all the five PCI slots are utilized, users can use the GPIOx (x=1~5, 0 is valid when an external PCI clock source is provided) for the use of General Purpose I/O. The optional use between PCI clock source and GPIO can be determined by the PCICLK_MASKx (x=0~5).
When PCICLK_MASKx (x=0~5) is set, the PCI clock output of the corresponding GPIOx is masked. The GPIOx then becomes a General Purpose I/O. Users then can arbitrarily specify the output enable control (GPIOx_OE) and the output value (GPIOxO) for the GPIOx.
GL9701 also provides a General Purpose I/O , GPIO6 (PIN65), for users to use. Unlike GPIO0~GPIO5, this pin does not Mux other functions. Users just have to control the output enable (GPIO6_OE) and its output value (GPIO6O).
5.4 Interrupt mapping
PCI INTx interrupts are "virtualized" in PCI Express using Assert_INTx and Deassert_INTx messages, where x is A, B, C, and D for the respective PCI INTx# interrupt signals defined in PCI 3.0. This message pairing provides a mechanism to preserve the level-sensitive semantics of the PCI interrupts. The Assert_INTx and Deassert_INTx messages transmitted on the PCI Express Link capture the asserting/deasserting edge of the respective PCI INTx# signal.
GL9701 is a multi-ported PCI Express bridge. A multi-ported PCI Express bridges must collapse the INTA#-INTD# pins from each of their downstream conventional PCI interface into four INTx "virtual wires" on their Upstream Port. The mapping between the INTx# pin on a PCI bus and the corresponding INTx messages on the PCI Express Link is based on the device number of the PCI bridge assigned to the port requesting the interrupt. The mapping is as follows:
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GL9701 PCI ExpressTM to PCI Bridge
Device Number of Conventional GL9701 Supporting Secondary Interface (Interrupt Source)
INTx# Interrupt Line from Mapping to INTx Virtual Downstream Conventional PCI Interface Wire on Primary Side of Bridge
INTA# INTB# 0, 4 INTC# INTD# INTA# INTB# 1 INTC# INTD# INTA# INTB# 2 INTC# INTD# INTA# INTB# 3 INTC# INTD#
INTA INTB INTC INTD INTB INTC INTD INTA INTC INTD INTA INTB INTD INTA INTB INTC
5.5 Initial Flow Control Advertisements
Flow control value for various credit type is advertised after the link is established. The initial value for each credit type in GL9701 is as followed:
Credit Type Posted Request headers (PH) Posted Request Data payload (PD) Non-Posted Request headers (NPH) Non-Posted Request Data payload (NPD) Completion headers (CPLH) Completion Data payload (CPLD)
Initial Flow Control Value 04h 20h 04h 04h 08h 20h
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GL9701 PCI ExpressTM to PCI Bridge 5.6 IDSEL Mapping
While receiving a Type1 Configuration Cycle from the upstream PCI Express port, GL9701 will convert it into a Type0 Configuration Cycle if the bus number is within the range specified by the Primary Bus Number Register and the Secondary Bus Number Register. The format of a Type0 Configuration Cycle is as followed:
GL9701 converts the destination ID device number to one of the AD[31:16] as the IDSEL of the five PCI slots. The mapping between the AD[31:16] and Device Number is:
Device Number [4:0] 00000 00001 00010 00011 00100 00101
AD[31:16] 0000_0000_0000_0001 0000_0000_0000_0010 0000_0000_0000_0100 0000_0000_0000_1000 0000_0000_0001_0000 0000_0000_0010_0000
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 6 Register Description
GL9701 implements the standard PCI Express-to-PCI Bridge configuration space format. Figure5.1 shows the capabilities supported by GL9701. Table5.1 and Table5.2 represent the configuration registers of GL9701 and their address byte offset values. Configuration register fields are assigned one of the attributes described in Table5.1.
Register Attribute HwInit
Description Hardware Initialized: Register bits are initialized by firmware or hardware mechanisms such as pin strapping or serial EEPROM. Bits are read-only after initialization and can only be reset (for write-once by firmware) with Fundamental Reset.
RO
Read-only register: Register bits are read-only and cannot be altered by software. Register bits may be initialized by hardware mechanisms such as pin strapping or serial EEPROM.
RW
Read-Write register: Register bits are read-write and may be either set or cleared by software to the desired state.
RW1C
Read-only status, Write-1-to-clear status register: Register bits indicate status when read, a set bit indicating a status event may be cleared by writing a 1. Writing a 0 to RW1C bits has no effect.
ROS
Sticky - Read-only register: Registers are read-only and cannot be altered by software. Registers are not initialized or modified by hot reset.
RWS
Sticky - Read-Write register: Registers are read-write and may be either set or cleared by software to the desired state. Bits are not initialized or modified by hot reset.
RW1CS
Sticky - Read-only status, Write-1-to-clear status register: Registers indicate status when read, a set bit indicating a status event may be cleared by writing a 1. Writing a 0 to RW1CS bits has no effect. Bits are not initialized or modified by hot reset.
RsvdP
Reserved and Preserved: Reserved for future RW
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GL9701 PCI ExpressTM to PCI Bridge
implementations; software must preserve value read for writes to bits. RsvdZ Reserved and Zero: Reserved for future RW1C implementations; software must use 0 for writes to bits.
Table 6.1Notation for attribute
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GL9701 PCI ExpressTM to PCI Bridge
0x00
0x3c 0x40
0x6c 0x70
0x80 0x84 0x90 0x94 0x98 0x9c
0xfc 0x100
0x148 0x150 0x158
Figure 6.1GL9701 Capabilities
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GL9701 PCI ExpressTM to PCI Bridge
Byte Offset Bit31 Device ID Status Class Code BIST Header Type Primary Latency Timer Base Address Register 0 Base Address Register 1 Secondary Latency timer Type1 Header Subordinate Bus Number Secondary Bus Number I/O Limit Primary Bus Number I/O Base 1Ch 20h 24h 28h 2Ch 30h 10h 14h 18h Vendor ID Command Revision ID Cache Line Size 0 00h 04h 08h 0Ch
Secondary Status Memory Limit Prefetchable Memory Limit
Memory Base Prefetchable Memory Base
Prefetchable Base Upper 32 Bits Prefetchable Limit Upper 32 Bits I/O Limit Upper 16 Bits Reserved I/O Base Upper 16 Bits
Capabilities Pointer 34h 38h Interrupt Line PCI Express Cap ID 70h 3Ch
Expansion ROM Base Address Bridge Control PCI Express Capabilities Register Interrupt Pin Next Cap Pointer
Device Capabilities PCI Express Capability Link Status Reserved Reserved Reserved Reserved Reserved Reserved Device Status Link Capabilities Link Control Device Control
74h 78h 7Ch 80h 84h 88h 8Ch 90h
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GL9701 PCI ExpressTM to PCI Bridge
Power Management Capability
Power Management Capability Next Pointer(43h) PM Capability ID 94h register Data PM Ctrl/Stat Bridge Ext Power Management Status and Control 98h
Table 6.2Legacy Configuration Space
PCI Express Extended Capabilities Space Advanced Error Reporting Capability Header Next Cap Pointer PCI Express Extended Capability ID Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Reporting Capability Header Log Register Advanced Error Capabilities and Control Register 118h 11Ch 120h 124h 128h Root Error Command -Not Implemented Root Error Status -Not Implemented 12Ch 130h 104h 108h 10Ch 110h 114h 100h
Correctable Error 134h Error Source ID Register -Not Implemented Source ID Register - Not Implemented Device Serial Number Capability PCI Express Enhanced Capability Header Serial Number Register (Lower DW) Serial Number Register (Upper DW) 150h 154h 158h
Table 6.3PCI Express Extended Configuration Space
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GL9701 PCI ExpressTM to PCI Bridge 6.1 Offset 00h: Device Identification
Generic configuration software will be able to determine what devices are available on PCI bus via these information. All of these registers are read-only.
Bits 15:0 31:16
Type RO RO
Default 17a0h 7163
Description Vendor ID: This field identifies the manufacturer of the device. Device ID: This field identifies the particular device.
6.2 Offset 04h: Command Register
Bits Type Default Description I/O Space: Controls a device's response to I/O Space accesses. 0 RW 0b 0- Disables the device response. 1- Allows the device torespond to I/O Space accesses. Memory Space: Controls a device's response to Memory Space 1 RW 0b accesses. 0- Disables the device response. 1- Allows the device to respond to Memory Space accesses. Bus Master: Controls a device's ability to act as a master on the 2 RW 0b PCI bus. 0- Disables the device from generating PCI accesses. 1- Allows the device to behave as a bus master. 3 RO 0b Special Cycles: Does not apply to PCI Express Bridge. Memory Write and Invalidate Enable: GL9701 does not 4 RO 0b optionally promote Memory Write Requests to Memory Write and Invalidate transactions on PCI. 5 RO 0b VGA Palette Snoop: Does not apply to PCI Express bridges. Parity Error Response: Controls the bridge's setting of the Master Data Parity Error bit in 6 RW 0b the Status register in response to a received poisoned TLP from PCI Express. 0 - Disables the setting of the Master Data Parity Error bit.
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GL9701 PCI ExpressTM to PCI Bridge
1- Enables the setting of the Master Data Parity Error bit. 7 RO 0b Reserved SERR# Enable: This bit enables reporting of non-fatal and fatal errors to the Root Complex. In addition, this bit enables transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages on behalf of SERR# assertions detected on the secondary interface. Note that errors are reported if 8 RW 0b enabled either through this bit or through the PCI Express specific bits in the Device Control register. 0 - Disable the reporting of bridge non-fatal errors and fatal errors to the Root Complex. 1 - Enable the reporting of bridge non-fatal errors and fatal errors to the Root Complex. 9 RO 0b Fast Back-to-Back Transactions Enable: Does not apply to PCI Express bridges. 10 RW 0b Interrupt Disable: GL9701 does not generate INTx interrupt messages on behalf of internal sources hence implements this bit as read-only with a value of 0. 15:11 RO 00h Reserved
6.3 Offset 06h: Status Register Bits
2:0 3
Type
RO RO
Default
0h 0b Reserved
Description
Interrupt Status - Indicates that an INTx interrupt message is pending on behalf of sources internal to the bridge.
4
RO
1b
Capabilities List - Indicates the presence of a Capability List item.
5 6 7
RO RO RO
0b 0b 0b
66 MHz Capable - Does not apply to PCI Express bridges. Reserved Fast Back-to-Back Transactions Capable - Does not apply to PCI Express bridges.
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GL9701 PCI ExpressTM to PCI Bridge
Master Data Parity Error - This bit is used to report the detection of uncorrectable data errors by the bridge. This bit is set if the Parity Error Response bit in the Command register is set and either of the following two conditions occur: The bridge receives a Completion with data marked 8 RW1C 0b poisoned on the primary interface. The bridge poisons a write Request on the primary interface. 0 - No uncorrectable data error detected on the primary interface. 1- Uncorrectable data error detected on the primary interface. 10:9 RO 00b DEVSEL# Timing - Does not apply to PCI Express bridges. Must be hardwired to 00b. Signaled Target-Abort - This bit is set when the bridge generates a completion with Completer Abort Completion Status in response to a request received on its primary interface. 11 RW1C 0b 0 - Completer Abort Completion not transmitted on the primary interface. 1 - Completer Abort Completion transmitted on the primary interface. Received Target-Abort - This bit is set when the bridge receives a Completion with Completer Abort Completion Status on its primary interface. 12 RW1C 0b 0 - Completer Abort Completion Status not received on primary interface. 1 - Completer Abort Completion Status received on primary interface. Received Master-Abort - This bit is set when the bridge receives a Completion with Unsupported Request Completion Status on its primary interface. 13 RW1C 0b 0 - Unsupported Request Completion Status not received on primary interface. 1 - Unsupported Request Completion Status received on primary interface.
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GL9701 PCI ExpressTM to PCI Bridge
Signaled System Error - This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL message to the Root Complex and the SERR# Enable bit in the Command register is 14 RW1C 0b set. 0 - Neither ERR_FATAL nor ERR_NONFATAL transmitted on primary interface. 1 - ERR_FATAL or ERR_NONFATAL transmitted on primary interface. Detected Parity Error - This bit is set by the bridge whenever it receives a poisoned TLP or, if supported, a TLP with bad ECRC (Read Completion or Write Request) on the primary interface, regardless of the state the Parity Error Response bit in the 15 RW1C 0b Command register. 0 - Data poisoning and bad ECRC not detected by the bridge on its primary interface. 1 - Data poisoning or bad ECRC detected by the bridge on its primary interface.
6.4 Offset 08h: Revision ID
Bits 7:0 Type RO Default 00h Description Revision ID: Indicates the die version of GL9701.
6.5 Offset 09h: Class Code
Bits 7:0 Type RO Default 00h Description Programming Interface (PIF): This bit indicates that this device is standard PCI-to-PCI Bridge. 15:8 RO 04h Sub Class Code (SCC): This 8-bit value indicates that this device is a PCI-to-PCI Bridge. 23:16 RO 06h Base Class Code (BCC): The value of 06h indicates that this is a bridge device.
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GL9701 PCI ExpressTM to PCI Bridge 6.6 Offset 0ch: Cache Line Size Register
Bits 7:0 Type RW Default 00h Description Cache Line Size: Specifies the system cacheline size in units of DWORDs.
6.7 Offset 0dh: Primary Latency Timer Register
Bits 7:0 Type RO Default 00h Description Primary Latency Timer: The primary/master latency timer does not apply to PCI Express bridges..
6.8 Offset 0eh: Header Type Register
Bits 7:0 Type RO Default 01h Description Header Type: Indicates that the header is compatible with PCI system software developed for Type 01h PCI and PCI-X bridges.
6.9 Offset 0fh: Bist Register
Bits 7:0 Type RO Default 00h Description BIST: GL9701 does not support BIST.
6.10 Offset 10h: Base Register0
Bits 31:0 Type RO Default 00h Description Base Register0: GL9701 does not use base register.
6.11 Offset 14h: Base Register1
Bits 31:0 Type RO Default 00h Description Base Register1: GL9701 does not use base register.
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GL9701 PCI ExpressTM to PCI Bridge 6.12 Offset 18h: Primary Bus Number Register
Bits Type Default Description Primary Bus Number: Used to record the Bus Number of the 7:0 RW 00h logical PCI bus segment to which the primary interface of the bridge is connected. Configuration software is required to program the value into this register..
6.13 Offset 19h: Secondary Bus Number Register
Bits Type Default Description Secondary Bus Number: Used to record the Bus Number of the 7:0 RW 00h PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register.
6.14 Offset 1ah: Subordinate Bus Number Register
Bits Type Default Description Subordinate Bus Number: Used to record the Bus Number of the 7:0 RW 00h highest numbered PCI bus segment which is downstream of (or subordinate to) the bridge. Configuration software programs the value in this register.
6.15 Offset 1bh: Secondary Latency Timer Register
Bits Type Default Description Secondary Latency Timer: This register specifies, in units of PCI 7:0 RW 00h bus clocks, the value of the Latency Timer for the secondary interface GL9701.
6.16 Offset 1ch: IO Base and IO Limit Register
Bits 3:0 Type RO Default 0h Description I/O Base Addressing Capability: Each of these bits is hard-wired
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GL9701 PCI ExpressTM to PCI Bridge
to 0, indicating support for 16-bit I/O addressing only. I/O Base Address Bits [15:12]: These bits define the bottom address of an address range to determine when to forward I/O 7:4 RW 0h transactions from one interface to another. These bits correspond to address lines[15:12] for 4 KB alignment. Bits[11:0] are assumed to be 000h. 11:8 RO 0h I/O Limit Addressing Capability (IOLC): Each of these bits is hard-wired to 0, indicating support for 16-bit I/O addressing only. I/O Limit Address Bits [15:12] (IOLA): These bits define the top address of an address range to determine when to forward I/O 15:12 RW 0h transactions from PCI Express* to PCI. These bits correspond to address lines[15:12] for 4 KB aligned window. Bits[11:0] are assumed to be FFFh.
6.17 Offset 1eh: Secondary Status Register
Bits 4:0 5 6 Type RsvdZ RO RsvdZ Default 00h 1b 0b Reserved 66 MHz Capable: This bit indicates that the secondary interface of the bridge is 66 MHz-capable. Reserved Fast Back-to-Back Transactions Capable: This bit indicates that 7 RO 0b the secondary interface is not able to receive fast back-to-back cycles. Master Data Parity Error - This bit is used to report the detection of an uncorrectable data error by the bridge. This bit is set if the bridge is the bus master of the transaction on the secondary interface, the Parity Error Response Enable bit in the 8 RW1C 0b Bridge Control register is set, and either of the following two conditions occur: The bridge asserts PERR# on a read transaction. The bridge detects PERR# asserted on a write transaction. Once set, this bit remains set until it is reset by writing a 1 to this Description
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GL9701 PCI ExpressTM to PCI Bridge
bit location. If the Parity Error Response Enable bit is set to zero, this bit will not be set when an error is detected. 0 - No uncorrectable data error detected on the secondary interface. 1 - Uncorrectable data error detected on the secondary interface. DEVSEL Timing - This bit field encodes the timing of the secondary interface DEVSEL# as listed below. 10:9 RO 01b 00 - Fast DEVSEL# decoding 01 - Medium DEVSEL# decoding 10 - Slow DEVSEL# decoding 11 - Reserved Signaled Target-Abort - This bit reports the signaling of a Target-Abort termination by the bridge when it responds as the 11 RW1C 0b target of a transaction on its secondary interface or when it signals a PCI-X Split Completion with Target-Abort. 0 - Target-Abort not signaled on secondary interface. 1 - Target-Abort signaled on secondary interface. Received Target-Abort - This bit reports the detection of a Target-Abort termination by the bridge when it is the master of a 12 RW1C 0b transaction on its secondary interface. 0 - Target-Abort not detected on secondary interface. 1 - Target-Abort detected on secondary interface. Received Master-Abort - This bit reports the detection of a Master-Abort termination by the bridge when it is the master of a 13 RW1C 0b transaction on its secondary interface. 0 - Master-Abort not detected on secondary interface. 1 - Master-Abort detected on secondary interface. Received System Error - This bit reports the detection of an SERR# assertion on the secondary interface of the bridge. 14 RW1C 0b 0 - SERR# assertion on the secondary interface has not been detected. 1 - SERR# assertion on the secondary interface has been detected.
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GL9701 PCI ExpressTM to PCI Bridge
Detected Parity Error - This bit reports the detection of an uncorrectable address, attribute, or data error by the bridge on its secondary interface. The bit is set irrespective of the state of the Parity Error 15 RW1C 0b Response Enable bit in the Bridge Control register. 0 - Uncorrectable address, attribute, or data error not detected on secondary interface 1 - Uncorrectable address, attribute, or data error detected on secondary interface
6.18 Offset 20h: Memory Base and Limit Register
Bits 3:0 Type RO Default 0h Reserved Memory Base: These bits are compared with bits[31:20] of the 15:4 RW 000h incoming address to determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 19:16 RO 0h Reserved Memory Limit: These bits are compared with bits[31:20] of the 31:20 RW 000h incoming address to determine the upper 1 MB-aligned value (exclusive) of the range. The incoming address must be less than this value. Description
6.19 Offset 24h: Prefetchable Memory Base and Limit Register
Bits 3:0 Type RO Default 0h Description 64-bit Indicator: These bits indicate that 64-bit addressing is not supported for the base. Prefetchable Memory Base: These bits are compared with 15:4 RW 000h bits[31:20] of the incoming address to determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value.
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GL9701 PCI ExpressTM to PCI Bridge
19:16
RO
0b
64-bit Indicator: These bits indicate that 64-bit addressing is not supported for the limit. Prefetchable Memory Limit: These bits are compared with
31:20
RW
000h
bits[31:20] of the incoming address to determine the upper 1 MB-aligned value (inclusive) of the range. The incoming address must be less than this value.
6.20 Offset 28h: Prefetchable Base Upper 32-bits Register
Bits 31:0 Type RO Default 0000-0000h Description Prefetchable Memory Base Upper 32bit: These bits indicate that full 64-bit addressing is not supported.
6.21 Offset 2ch: Prefetchable Limit Upper 32-bits Register
Bits 31:0 Type RO Default 0000-0000h Description Prefetchable Memory Limit Upper 32bit: These bits indicate that full 64-bit addressing is not supported.
6.22 Offset 30h: IO Base and Limit Upper 16-bits Register
Bits 15:0 31:16 Type RO RO Default 0000h 0000h Description I/O Base Upper 16 Bits: 32-bit IO addressing is not supported I/O Limit Upper 16 Bits: 32-bit IO addressing is not supported
6.23 Offset 34h: Capabilities Pointer Register
Bits Type Default Description Capabilities Pointer: These bits indicate that the pointer for the 7:0 RO 70h first entry in the capabilities list is at 70h in the configuration space.
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GL9701 PCI ExpressTM to PCI Bridge 6.24 Offset 3ch: Interrupt Line Register
Bits Type Default Description Interrupt Line: Used to communicate interrupt line routing 7:0 RW 00h information. Software will write the routing information into this register as it initializes and configures the system.
6.25 Offset 3dh: Interrupt Pin Register
Bits 7:0 Type RO Default 00h Description Interrupt Pin: GL9701 does not use an interrupt pin.
6.26 Offset 3eh: Bridge Control Register
Bits Type Default Description Parity Error Response Enable - Controls the bridge's response to uncorrectable address, attribute, and data errors on the secondary interface. 0 RW 0b 0 - Ignore uncorrectable address, attribute, and data errors on the secondary interface. 1 - Enable uncorrectable address, attribute, and data error detection and reporting on the secondary interface. SERR# Enable - Controls the forwarding of secondary interface SERR# assertions to the primary interface. The bridge will transmit an ERR_FATAL or ERR_NONFATAL cycle on the primary interface when all of the following are true: SERR# is asserted on the secondary interface. 1 RW 0b This bit is set or Advanced Error Reporting is supported and the SERR# Assertion Detected Mask bit is clear in the Secondary Uncorrectable Error Mask register. The SERR# Enable bit is set in the Command register or the PCI Express-specific bits are set (refer to Chapter 10 for details) in the Device Control register of the PCI Express Capability Structure.
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GL9701 PCI ExpressTM to PCI Bridge
0 - Disable the forwarding of SERR# from the secondary interface to ERR_FATAL and ERR_NONFATAL 1- Enable the forwarding of secondary SERR# to ERR_FATAL or ERR_NONFATAL. ISA Enable - Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions will be forwarded if they address the last 768 bytes in 2 RW 0b each 1-KB block. 0 - Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers.
1- Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block).
VGA Enable (Optional) - Modifies the response of the bridge to VGA-compatible addresses. If this bit is set, the bridge will forward the following accesses on the primary interface to the secondary interface (and, conversely, block the forwarding of these addresses from the secondary to primary interface): Memory accesses in the range 000A 0000h to 000B FFFFh 3 RW 0b I/O addresses in the first 64 KB of the I/O address space (Address[31:16] for PCI Express are 0000h) and where Address[9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA address aliases - Address[15:10] may possess any value and is not used in the decoding) 0 - Do not forward VGA compatible memory and I/O addresses from the primary to the secondary interface
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GL9701 PCI ExpressTM to PCI Bridge
(addresses defined above) unless they are enabled for forwarding by the defined I/O and memory address ranges. 1- Forward VGA compatible memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (if the I/O Enable and Memory Enable bits are set) independent of the I/O and memory address ranges and independent of the ISA Enable bit. VGA 16-bit Decode - This bit enables the bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB. This bit only has meaning if the VGA Enable bit in this register is also set to 1, 4 RW 0b enabling VGA I/O decoding and forwarding by the bridge. 0 - Execute 10-bit address decodes on VGA I/O accesses. 1- Execute 16-bit address decodes on VGA I/O accesses. Master-Abort Mode - Controls the behavior of a bridge when it receives a Master-Abort termination (e.g., an Unsupported Request on PCI Express) on either interface. 0 - Do not report Master-Aborts. When a UR response is received from PCI Express for non-posted transactions, and when the secondary side is operating in conventional PCI mode, return FFFF FFFFh on reads and complete I/O writes normally. When a Master-Abort is received on the 5 RW 0b secondary interface for posted transactions initiated from the primary interface, no action is taken (i.e., all data is discarded). 1 - Report UR Completions from PCI Express by signaling Target-Abort on the secondary interface when the secondary interface is operating in conventional PCI mode. For posted transactions initiated from the primary interface and Master-Aborted on the secondary interface, the bridge must return an ERR_NONFATAL (by default)
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GL9701 PCI ExpressTM to PCI Bridge
or ERR_FATAL transaction (provided the SERR# Enable bit is set in the Command register). The severity is selectable only if Advanced Error Reporting is supported. Secondary Bus Reset - Forces the assertion of RST# on the secondary interface. 6 RW 0b 0 - Do not force the assertion of the secondary interface RST#. 1 - Force the assertion of the secondary interface RST#. Fast Back-to-Back Enable - Controls ability of the bridge to generate fast back-to-back transactions to different devices on the secondary interface. 7 RO 0b 0 - Disable generation of fast back-to-back transactions on the secondary interface. 1 - Enable generation of fast back-to-back transactions on the secondary interface. 8 RO 0b Primary Discard Timer - Does not apply to PCI Express. Secondary Discard Timer - When in conventional PCI mode, elects the number of PCI clocks that the bridge will wait for a master on the secondary interface to repeat a Delayed Transaction 9 RW 0b request 0 - The Secondary Discard Timer counts 215 PCI clock cycles. 1- The Secondary Discard Timer counts 210 PCI clock cycles. Discard Timer Status - This bit is set to a 1 when the Secondary Discard Timer expires and a Delayed Completion is discarded 10 RW 0b from a queue in the bridge. 0 - No discard timer error. 1 - Discard timer error. Discard Timer SERR# Enable - This bit enables the bridge to generate either an ERR_NONFATAL (by default) or 11 RW 0b ERR_FATAL transaction on the primary interface when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge.
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GL9701 PCI ExpressTM to PCI Bridge
0 - Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a result of the expiration f the Secondary Discard Timer. Note that an error message can still be sent if Advanced Error Reporting is supported and the Delayed Transaction Discard Timer Expired Mask bit is clear. 1 - Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge. 15:12 RO 0h Reserved
6.27 Offset 70h: PCI Express Capability List Register
Bits Type Default Description Capability ID - Indicates the PCI Express Capability structure. 7:0 RO 10h This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure. 15:8 RO 94h Next Capability Pointer - The offset to the next PCI capability structure which is Power Management Capability.
6.28 Offset 72h: PCI Express Capabilities Register
Bits 3:0 Type RO Default 1h Description Capability Version - Indicates PCI-SIG defined PCI Express capability structure version number. 7:4 8 13:9 RO RO RO 7h 0b 00h Device/Port Type - Indicates the type of PCI Express logical device. GL9701 is a PCI Express-to-PCI/PCI-X Bridge(7h). Slot Implemented - Not supported in GL9701. Interrupt Message Number - Not supported in GL9701.
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GL9701 PCI ExpressTM to PCI Bridge 6.29 Offset 74h: PCI Express Device Capabilities Register
Bits 2:0 Type RO Default 010b Description Max_Payload_Size Supported -512 bytes max payload size is supported. Phantom Functions Supported -No function number bits used 4:3 RO 00b for Phantom Functions; device may implement all function numbers. 5 RO 0b Extended Tag Field Supported -5-bit Tag field supported Endpoint L0s Acceptable Latency -The acceptable total latency 8:6 RO 111b that an Endpoint can withstand due to the transition from L0s state to the L0 state is more than 4 s. Endpoint L1 Acceptable Latency -The acceptable latency that an 11:9 RO 111b Endpoint can withstand due to the transition from L1 state to the L0 state is more than 64 s. 12 13 14 17:15 RO RO RO RsvdP 0b 0b 0b 000b Attention Button Present - Not supported. Attention Indicator Present - Not supported. Power Indicator Present - Not supported. RsvdP Captured Slot Power Limit Value - In combination with the Slot 25:18 RO 00h Power Limit Scale value, specifies the upper limit on power supplied by slot. This value is set by the Set_Slot_Power_Limit Message Captured Slot Power Limit Scale - Specifies the scale used for 27:26 RO 00b the Slot Power Limit Value. This value is set by the Set_Slot_Power_Limit Message.
6.30 Offset 78h: PCI Express Device Control Register
Bits 0 Type RW Default 0b Description Correctable Error Reporting Enable - This bit controls reporting of correctable errors.
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GL9701 PCI ExpressTM to PCI Bridge
Non-Fatal Error Reporting Enable - This bit controls reporting of Non-fatal errors. 2 RW 0b Fatal Error Reporting Enable - This bit controls reporting of Fatal errors. 3 RW 0b Unsupported Request Reporting Enable - This bit enables reporting of Unsupported Requests when set. Enable Relaxed Ordering - If this bit is set, the device is 4 RW 0b permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering. Max_Payload_Size - This field sets maximum TLP payload 7:5 RW 000b size for the device. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported in the Device Capabilities register. 8 9 10 11 RO RO RO RO 0b 0b 0b 0b Extended Tag Field Enable - Not supported. Phantom Functions Enable - Not supported. Auxiliary (AUX) Power PM Enable - Not su[pported. Enable No Snoop - GL9701 never sets the No Snoop attribute in transactions it initiates. Max_Read_Request_Size - This field sets the maximum Read 14:12 RW 010b Request size for the Device as a Requester. The Device must not generate read requests with size exceeding the set value. 15 RsvdP 0b RsvdP
1
RW
0b
6.31 Offset 7ah: PCI Express Device Status Register
Bits Type Default Description Correctable Error Detected - This bit indicates status of 0 RW1C 0b correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Non-Fatal Error Detected - This bit indicates status of Nonfatal 1 RW1C 0b errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the
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GL9701 PCI ExpressTM to PCI Bridge
Device Control register. Fatal Error Detected - This bit indicates status of Fatal errors 2 RW1C 0b detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Unsupported Request Detected - This bit indicates that the 3 RW1C 0b device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 4 RO 0b AUX Power Detected - Devices that require AUX power report this bit as set if AUX power is detected by the device. Transactions Pending - This bit when set indicates that the device has issued Non-Posted Requests which have not been 5 RO 0b completed. A device reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. 15:6 RsvdZ 000h RsvdZ
6.32 Offset 7ch: PCI Express Link Capabilities Register
Bits Type Default Description Maximum Link Speed - This field indicates the maximum Link 3:0 RO 0001b speed of the given PCI Express Link. Defined encodings are: 0001b 9:4 RO 00001b 2.5 Gb/s Link
Maximum Link Width - This field indicates the maximum width of the given PCI Express Link.
11:10
RO
00b
Active State Power Management (ASPM) Support - Not supported
14:12
RO
111b
L0s Exit Latency - This field indicates the L0s exit latency for the given PCI Express Link.
17:15 23:18 31:24
RO RsvdP RO
111b 00h 01h
L1 Exit Latency - This field indicates the L1 exit latency for the given PCI Express Link. RsvdP Port Number - This field indicates the PCI Express Port
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GL9701 PCI ExpressTM to PCI Bridge
number for the given PCI Express Link.
6.33 Offset 80h: PCI Express Link Control Register
Bits 1:0 2 Type RO RsvdP Default 00b 0b Description Active State Power Management (ASPM) Control - GL9701 does not support ASPM. RsvdP Read Completion Boundary (RCB) - Indicates the RCB value 3 RO 0b for the Root Port. Defined encodings are: 0b : 64 byte 1b : 128 byte 4 5 RW RW 0b 0b Link Disable - This bit disables the Link when set to 1b. Retrain Link - A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. Common Clock Configuration - This bit when set indicates that this component and the component at the opposite end of 6 RW 0b this Link are operating with a distributed common reference clock. A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock. Extended Synch - This bit when set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a single SKP 7 RW 0b ordered set prior to entering the L0 state, and the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the Recovery state. 15:8 RsvdP 00h RsvdP
6.34 Offset 82h: PCI Express Link Status Register
Bits 3:0 Type RO Default 0h Description Link Speed - This field indicates the negotiated Link speed of the given PCI Express Link.Defined encodings are:
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GL9701 PCI ExpressTM to PCI Bridge
0001b 2.5 Gb/s PCI Express Link 9:4 RO 000001b Negotiated Link Width - This field indicates the negotiated width of the given PCI Express Link. 10 RO 0b Training Error - This read-only bit indicates that a Link training error occurred. Link Training - This read-only bit indicates that Link training is in progress (Physical Layer LTSSM in Configuration or 11 RO 0b Recovery state) or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit once Link training is complete. Slot Clock Configuration - This bit indicates that the 12 RO 1b component uses the same physical reference clock that the platform provides on the connector. 15:13 RsvdZ 000b RsvdZ
6.35 Offset 94h: PM Capability ID Register
Bits 7:0 Type RO Default 01h Description ID - This field, when "01h" identifies the linked list item as being the PCI Power Management registers.
6.36 Offset 95h: PM Next Pointer Register
Bits 7:0 Type RO Default a0h Description Next Item Pointer - Next capability is Slot Numbering capability.
6.37 Offset 96h: Power Management Capabilities Register
Bits Type Default Description Version - A value of 010b indicates that this function complies 2:0 RO 010b with Revision 1.1 of the PCI Power Management Interface Specification. 3 RO 0b PME Clock - Indicates that no PCI clock is required for the
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GL9701 PCI ExpressTM to PCI Bridge
function to generate PME#. 5:4 8:6 9 10 15:11 RO RO RO RO RO 00b 111b 1b 1b Reserved Aux_Current - This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. D1_Support - GL9701 supports the D1 Power Management State. D2_Support - GL9701 supports the D1 Power Management State.
00001b PME_Support - PME# can be asserted from D0.
6.38 Offset 98h: Power Management Control and Status Register
Bits Type Default Description PowerState - This 2-bit field is used both to determine 1:0 RW 00b the current power state of a function and to set the function into a new power state. 7:2 8 RO RW 000000b Reserved 0b PME_En - A "1" enables the function to assert PME#. When "0", PME# assertion is disabled. 12:9 RO 0h Data_Select - This 4-bit field is used to select which data is to be reported through the Data register and Data_Scale field. Data_Scale - This 2-bit read-only field indicates the 14:13 RO 00b scaling factor to be used when interpreting the value of the Data register. PME_Status - This bit is set when the function would normally 15 RW1C 0b assert the PME# signal independent of the state of the PME_En bit.
6.39 Offset a0h: Slot Numbering Capabilities ID Register
Bits 7:0 Type RO Default 04h Description Slot Numbering Capabilities ID Register
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GL9701 PCI ExpressTM to PCI Bridge 6.40 Offset a1h: Slot Numbering Pointer to Next ID Register
Bits 7:0 Type RO Default 00h Description Pointer to Next Capabilities
6.41 Offset a2h: Slot Numbering Expansion Slot Register
Bits Type Default Description Expansion Slots Provided - Contains the binary value of the 4:0 RO 3h number of PCI expansion slots located directly on the secondary interface of this bridge. First in Chassis - If this bit is set, it indicates that this bridge is the first in an expansion chassis. A bridge with this bit set 5 RO 1b indicates the existence of an expansion chassis that requires a unique chassis number. 0 - This is not a parent bridge. 1 - This is a parent bridge. 7:6 RO 00b Reserved
6.42 Offset a3h: Slot Numbering Chassis Number Register
Bits 7:0 Type RW Default 00h Description Chassis Number: Contains the physical chassis number for the slots on the bridge's secondary interface.
6.43 Offset 100h: Advanced Error Reporting Enhanced Capability Header Register
Bits 15:0 19:16 31:20 Type RO RO RO Default 0001h 1h 150h Description PCI Express Extended Capability ID Capability Version Next Capability Offset - Next capability is Device Serial Number Capability.
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GL9701 PCI ExpressTM to PCI Bridge 6.44 Offset 104h: Uncorrectable Error Status Register
Bits 0 4 12 13 14 15 16 17 18 19 20 Type RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C Default 0 0 0 0 0 0 0 0 0 0 0 Training Error Status Data Link Protocol Error Status Poisoned TLP Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed TLP Status ECRC Error Status Unsupported Request Error Status Description
6.45 Offset 108h: Uncorrectable Error Mask Register
Bits 0 4 12 13 14 15 16 17 18 19 Type RWS RWS RWS RWS RWS RWS RWS RWS RWS RWS Default 0 0 0 0 0 0 0 0 0 0 Training Error Mask Data Link Protocol Error Mask Poisoned TLP Mask Flow Control Protocol Error Mask Completion Timeout Mask Completer Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask ECRC Error Mask Description
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GL9701 PCI ExpressTM to PCI Bridge
20
RWS
0
Unsupported Request Error Mask
6.46 Offset 10ch: Uncorrectable Error Severity Register
Bits 0 4 12 13 14 15 16 17 18 19 20 Type RWS RWS RWS RWS RWS RWS RWS RWS RWS RWS RWS Default 1 1 0 1 0 0 0 1 1 0 0 Training Error Severity Data Link Protocol Error Severity Poisoned TLP Severity Flow Control Protocol Error Severity Completion Timeout Error Severity Completer Abort Error Severity Unexpected Completion Error Severity Receiver Overflow Error Severity Malformed TLP Severity ECRC Error Severity Unsupported Request Error Severity Description
6.47 Offset 110h: Correctable Error Status Register
Bits 0 6 7 8 12 Type RW1CS RW1CS RW1CS RW1CS RW1CS Default 0 0 0 0 0 Receiver Error Status Bad TLP Status Bad DLLP Status REPLAY_NUM Rollover Status Replay Timer Timeout Status Description
6.48 Offset 114h: Correctable Error Mask Register
Bits Type Default Description
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GL9701 PCI ExpressTM to PCI Bridge
0 6 7 8 12
RWS RWS RWS RWS RWS
0 0 0 0 0
Receiver Error Mask Bad TLP Mask Bad DLLP Mask REPLAY_NUM Rollover Mask Replay Timer Timeout Mask
6.49 Offset 118h: Advanced Error Capabilities and Control Register
Bits 4:0 Type ROS Default 00h Description First Error Pointer - Identifies the bit position of the first error reported in the Uncorrectable Error Status register. 5 RO 1b ECRC Generation Capable - This bit indicates that the device is capable of generating ECRC. 6 RWS 0b ECRC Generation Enable - This bit when set enables ECRC generation. 7 RO 1b ECRC Check Capable - This bit indicates that the device is capable of checking ECRC. 8 RWS 0b ECRC Check Enable - This bit when set enables ECRC checking.
6.50 Offset 11ch: Header Log Register
Bits 127:0 Type ROS Default 0h Description Header Log - Header of TLP associated with error
6.51 Offset 12ch: Secondary Uncorrectable Error Status Register
Bits 0 1 2 Type RW1CS RW1CS RW1CS Default 0 0 0 Description Target-Abort on Split Completion Status Master-Abort on Split Completion Status Received Target-Abort Status
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GL9701 PCI ExpressTM to PCI Bridge
3 4 5 6 7 8 9 10 11 12 13
RW1CS RsvdZ RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS
0 0 0 0 0 0 0 0 0 0 0
Received Master-Abort Status Reserved Unexpected Split Completion Error Status Uncorrectable Split Completion Message Data Error Status Uncorrectable Data Error Status Uncorrectable Attribute Error Status Uncorrectable Address Error Status Delayed Transaction Discard Timer Expired Status PERR# Assertion Detected SERR# Assertion Detected (No Header Log) Internal Bridge Error Status
6.52 Offset 130h: Secondary Uncorrectable Error Mask Register
Bits 0 1 2 3 4 5 6 7 8 9 Type RWS RWS RWS RWS RsvdP RWS RWS RWS RWS RWS Default 0 0 0 1 0 1 0 1 1 1 Description Target-Abort on Split Completion Mask Master-Abort on Split Completion Mask Received Target-Abort Mask Received Master-Abort Mask Reserved Unexpected Split Completion Error Mask Uncorrectable Split Completion Message Data Error Mask Uncorrectable Data Error Mask Uncorrectable Attribute Error Mask Uncorrectable Address Error Mask
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GL9701 PCI ExpressTM to PCI Bridge
10 11 12 13
RWS RWS RWS RWS
1 0 1 0
Delayed Transaction Discard Timer Expired Mask PERR# Assertion Detected Mask SERR# Assertion Detected Mask Internal Bridge Error Mask
6.53 Offset 134h: Secondary Uncorrectable Error Severity Register
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Type RWS RWS RWS RWS RsvdP RWS RWS RWS RWS RWS RWS RWS RWS RWS Default 0 0 0 0 0 0 1 0 1 1 0 0 1 0 Description Target-Abort on Split Completion Severity Master-Abort on Split Completion Severity Received Target-Abort Severity Received Master-Abort Severity Reserved Unexpected Split Completion Error Severity Uncorrectable Split Completion Message Data Error Severity Uncorrectable Data Error Severity Uncorrectable Attribute Error Severity Uncorrectable Address Error Severity Delayed Transaction Discard Timer Expired Severity PERR# Assertion Detected Severity SERR# Assertion Detected Severity Internal Bridge Error Severity
6.54 Offset 138h: Secondary Error Capabilities and Control Register
Bits Type Default Description
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GL9701 PCI ExpressTM to PCI Bridge
4:0
ROS
00h
Secondary Uncorrectable First Error Pointer
6.55 Offset 13ch: Secondary Header Log Register
Bits 35:0 Type ROS Default 0h Description Transaction Attribute - Not supported. Transaction Command Lower - The 4-bit value transferred on 39:36 ROS 0h C/BE[3:0]# during the first address phase. 43:40 127:64 ROS ROS 0h 0h Transaction Command Upper - Not supported Transaction Address - bits 127:96 will be set to zero
6.56 Offset 150h: Device Serial Number Enhanced Capability Header Register
Bits 15:0 19:16 31:20 Type RO RO RO Default 0003h 1h 000h Description PCI Express Extended Capability ID Capability Version Next Capability Offset
6.57 Offset 154h: Device Serial Number Register
Bits 63:0 Type RO Default 0h Description PCI Express Device Serial Number
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 7 Electrical Characteristics
7.1 Operation Conditions
Symbol
VDD VDD33 VDD18_AUX VDD33_AUX AVDDPCI VDDPLL VDDRX VDDTX
Parameter
Non-AUX GL9701 Bridge Core Power Non-AUX PCI Pad Power AUX GL9701 Bridge Core Power AUX PCI Pad Power Analog Power for PCI PLL Analog power for PLL Analog Power for RX Analog Power for TX
Min.
1.62 2.97 1.62 2.97 1.62 1.62 1.62 1.62
Typ.
1.8 3.3 1.8 3.3 1.8 1.8 1.8 1.8
Max.
1.98 3.63 1.98 3.63 1.98 1.98 1.98 1.98
Unit
Volt Volt Volt Volt Volt Volt Volt Volt
7.2 Differential Transmitter (TX) Output Specification
The following table defines the specification of parameters for the differential output at all Transmitters (TXs). The parameters are specified at the component pins. Symbol UI Parameter Unit Interval Min 399.88 Typ 400 Max 400.12 Units ps Comments Each UI is 400 ps +/-300 ppm. UI does not account for SSC dictated variations. See Note 1. VTX-DIFFp-p Differential Peak to Peak Output Voltage VTX-DE-RATIO De-Emphasized Differential Output Voltage (Ratio) -3.0 -3.5 -4.0 dB This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. 0.800 1.2 V VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-| See Note 2.
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GL9701 PCI ExpressTM to PCI Bridge
See Note 2. TTX-EYE Minimum TX Eye Width 0.75 UI The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - TTX-EYE = 0.25 UI. This parameter is measured with the equivalent of a zero jitter reference clock. See Notes 2 and 3. TTX-EYEMEDIANto-MAXJITTER Maximum time between the jitter median and maximum deviation from the median. 0.125 UI Jitter is defined as the measurement variation of the crossing points (VTX-DIFF = 0 V) in relation to recovered TX UI. To be measured after the clock recovery function. See Notes 2 and 3. TTX-RISE, TTX-FALL D+/D- TX Output Rise/Fall Time VTX-CM-ACp RMS AC Peak Common Mode Output Voltage 20 mV VTX-CM-ACp = RMS(|VTX-D+ + VTX-D-|/2 - VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ +VTX-D-|/2 See Note 2. VTX-CM-DCACTIVEIDLEDELTA Absolute Delta of DC Common 0 100 mV |VTX-CM-DC [during L0] - VTX-CM-Idle0.125 UI See Notes 2 and 5.
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GL9701 PCI ExpressTM to PCI Bridge
Mode Voltage During L0 and Electrical Idle. DC[During Electrical Idle.]| <= 100 mV VTX-CM-DC = DC(avg) of |VTX-D+ +VTX-D-|/2 [L0] VTX-CM-Idle-DC= DC(avg) of |VTX-D++ VTX-D-|/2 [Electrical Idle] See Note 2. VTX-CM-DCLINEDELTA Absolute Delta of DC Common Mode Voltage between D+ and D0 25 mV |VTX-CM-DC-D+ - VTX-CM-DC-D-| <=25 mV VTX-CM-DC-D+ = DC(avg) of |VTX-D+| VTX-CM-DC-D- = DC(avg) of |VTX-D-| See Note 2. VTX-IDLE-DIFFp Electrical Idle Differential Peak Output Voltage 0 20 mV VTX-IDLE-DIFFp = |VTX-Idle-D+ VTx-Idle-D-| <= 20 mV See Note 2. VTX-RCVDETECT The amount of voltage change allowed during Receiver Detection 600 mV The total amount of voltage change that a Transmitter can apply to sense whether a low impedance Receiver is present. VTX-DC-CM The TX DC Common Mode Voltage 0 3.6 V The allowed DC Common Mode voltage under any conditions.
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GL9701 PCI ExpressTM to PCI Bridge
TX Short Circuit Current Limit 90 mA The total current the Transmitter can provide when shorted to its ground. TTX-IDLE-MIN Minimum time spent in Electrical Idle 50 UI Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set. TTX-IDLE-SETTOIDLE Maximum time to transition to a valid Electrical Idle after sending an Electrical Idle ordered set 20 UI After sending an Electrical Idle ordered set, the Transmitter must meet all Electrical Idle specifications within this time. This is considered a debounce time for the Transmitter to meet Electrical Idle after transitioning from L0. TTX-IDLE-TODIFFDATA Maximum time to transition to valid TX specifications after leaving an 20 UI Maximum time to meet all TX specifications when transitioning from Electrical Idle to
ITX-SHORT
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GL9701 PCI ExpressTM to PCI Bridge
Electrical Idle condition sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving Electrical Idle. RLTX-DIFF Differential Return Loss 10 dB Measured over 50 MHz to 1.25 GHz. See Note 4. RLTX-CM Common Mode Return Loss 6 dB Measured over 50 MHz to 1.25 GHz. See Note 4. ZTX-DIFF-DC DC Differential TX Impedance 80 100 120 TX DC Differential Mode low impedance. See Note 6. LTX-SKEW Lane-to-Lane Output Skew 500 + 2 UI ps Static skew between any two Transmitter Lanes within a single Link. CTX AC Coupling Capacitor 75 200 nF All Transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. Tcrosslink Crosslink Random Timeout 0 1 ms This random timeout helps resolve conflicts in crosslink configuration
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GL9701 PCI ExpressTM to PCI Bridge
by eventually resulting in only one Downstream and one Upstream Port. Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load and measured using the clock recovery function. 3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the Transmitter using the clock recovery function. The TTX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget using the clock recovery function. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. This parameter is measured with the equivalent of a zero jitter reference clock. The TTX-EYE measurement is to be met at the target bit error rate. The TTX-EYE-MEDIAN-to-MAX-JITTER is to be met using the compliance pattern at a sample size of 1,000,000 UI. 4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 10 dB with a differential test input signal no less than 200 mV (peak value, 400 mV differential peak to peak) swing around ground applied to D+ and D- lines and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line. Note that the series capacitors CTX is optional for the return loss measurement. 5. Measured between 20-80% at Transmitter package pins into a test load for both VTX-D+ and VTX-D-. 6. ZTX-DIFF-DC is the small signal resistance of the transmitter measured at a DC operating point that is equivalent to that established by connecting a 100 resistor from D+ and D- while the TX is driving a static logic one or logic zero. Equivalently, this parameter can be derived by measuring the RMS voltage of the TX while transmitting a test pattern into two different differential terminations that are near 100 . Small signal resistance is measured by forcing a small change in differential voltage and dividing this by the corresponding change in current.
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GL9701 PCI ExpressTM to PCI Bridge 7.3 Differential Receiver (RX) Input Specification
The following table defines the specification of parameters for all differential Receivers (RXs). The parameters are specified at the component pins. Symbol Parameter Unit Interval Min 399.88 Typ 400 Max Units 400.12 ps Comments The UI is 400 ps +/- 300 ppm. UI does not account for SSC dictated variations. See Note 7. VRX-DIFFp-p Differential Input Peak to Peak Voltage TRX-EYE Minimum Receiver Eye Width 0.4 UI 0.175 1.2 V VRX-DIFFp-p = 2*|VRX-D+ -VRX-D-| See Note 8. The maximum interconnect media and Transmitter jitter that can be tolerated by the Receiver can be derived as TRX-MAX-JITTER = 1 - TRX-EYE = 0.6 UI. See Notes 8, 9, and 10. TRX-EYE-MEDI AN-toMAX-JITTER Maximum time between the jitter median and maximum deviation from the median. 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered TX UI. To be measured after the clock recovery function. See Notes 8 and 9. VRX-CM-ACp AC Peak Common Mode Input Voltage 150 mV VRX-CM-AC = |VRX-D+ + VRX-D-|/2 - VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D++ VRX-D-|/2 See Note 8. RLRX-DIFF Differential Return Loss 10 dB Measured over 50 MHz to 1.25 GHz. See Note 11. RLRX-CM Common Mode 6 dB Measured over 50 MHz to
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GL9701 PCI ExpressTM to PCI Bridge
Return Loss 1.25 GHz. See Note 11. ZRX-DIFF-DC DC Differential Input Impedance ZRX-DC DC Input Impedance 40 50 60 80 100 120 RX DC Differential Mode impedance. See Note 12. Required RX D+ as well as D- DC impedance (50 +/- 20% tolerance). See Notes 8 and 12. ZRX-HIGH-IMPDC Powered Down DC Input Impedance 200k Required RX D+ as well as D- DC impedance when the Receiver terminations do not have power. See Note 13. VRX-IDLE-DETDIFFp-p Electrical Idle Detect Threshold 65 175 mV VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ - VRX-D-| Measured at the package pins of the Receiver. TRX-IDLE-DETDIFFENTERTIM E Unexpected Electrical Idle Enter Detect Threshold Integration Time 10 ms An unexpected Electrical Idle (VRX-DIFFp-p < VRX-IDLEDET- DIFFp-p) must be recognized no longer than TRX-IDLE-DET-DIFF-ENTERTIM E to signal an unexpected idle condition. LRX-SKEW Total Skew 20 ns Skew across all Lanes on a Link. This includes variation in the length of a SKP ordered set (e.g., COM and one to five SKP Symbols) at the RX as well as any delay differences arising from the interconnect itself. 7. No test load is necessarily associated with this value. 8. Specified at the measurement point and measured using the clock recovery function. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered using the clock recovery function specified in Section 4.3.3.2 must be used as a reference for the eye diagram. 9. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.64. It should be noted that the median
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is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. The RX UI recovered using the clock recovery function must be used as the reference for the eye diagram. This parameter is measured with the equivalent of a zero jitter reference clock. The TRX-EYE measurement is to be met at the target bit error rate. The TRX-EYE-MEDIAN-to-MAX-JITTER specification is to be met using the compliance pattern at a sample size of 1,000,000 UI. 10. See the PCI Express Jitter and BER white paper for more details on the Rx-Eye measurement. 11. The Receiver input impedance shall result in a differential return loss greater than or equal to 10 dB with a differential test input signal of no less than 200 mV (peak value, 400 mV differential peak to peak) swing around ground applied to D+ and D- lines and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 to ground for both the D+ and D- line. Note that the series capacitors CTX is optional for the return loss measurement. 12. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port. 13. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be measured at 200 mV above the RX ground.
7.4 PCI Interface DC Specifications
Symbol Vcc Vih Vil Vipu Parameter Supply Voltage Input High Voltage Input Low Voltage Input Pull-up Voltage Iil Input Leakage Current Voh Vol Cin Output High Voltage Iout = -500A Output Low Voltage Iout = 1500A Input Pin Capacitance Cclk CLK Pin 5 12 pF 0.9Vcc 0.1Vcc 10 V V pF 3 0 < Vin < Vcc +10 A 2 Condition Min. 3.0 0.5Vcc -0.5 0.7Vcc Max 3.6 Vcc + 0.5 0.3Vcc Units V V V V 1 Notes
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Capacitance CIDSEL IDSEL Pin Capacitance Lpin IOff Pin Inductance PME# input leakage Vo 3.6 V Vcc off or floating 20 1 nH A 5 6 8 pF 4
Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization must assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK, SMBDAT, and SMBCLK) with an exception granted to system board-only devices up to 16 pF in order to accommodate PGA packaging. This would mean, in general, that components for add-in cards need to use alternatives to ceramic PGA packaging; i.e., PQFP, SGA, etc. Pin capacitance for SMBCLK and SMBDAT is not specified; however, the maximum capacitive load is specified for the add-in card in Section 8.2.5. 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 5. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet. 6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power is removed from Vcc of the component. This assumes that no event has occurred to cause the device to attempt to assert PME#.
7.5 PCI Interface AC Specifications
Symbol Ioh(AC) Parameter Switching Current High Condition 0 < Vout 0.3Vcc 0.3VccVout 0.6Vcc 0.6Vcc>Vout>0.1Vcc 0.18Vcc>Vout>0 16Vcc 26.7Vout Eqt'n D Min. -12Vcc -17.1(Vcc-Vout) Eqt'n C mA mA Max Units mA mA Notes 1 1 1, 2 1 1 1, 2
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GL9701 PCI ExpressTM to PCI Bridge
Low Clamp Current Ich High Clamp Current slewr Output Rise Slew Rate slewf Output Fall Slew Rate 0.6Vcc - 0.2Vcc load 1 4 V/ns 3 0.2Vcc - 0.6Vcc load 1 4 V/ns 3 Vcc+4 > Vin Vcc+1 25+(Vin-Vcc-1)/0.015 mA -3 < Vin -1 -25+(Vin+1)/0.015 mA
Icl
7.6 Clock and Reset Specifications
Symbol Tcyc Thigh Tlow Notes:
Parameter CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate RST#SlewRate
Min 30 11 11 1 50
Max
Units ns ns ns
Notes 1
4 -
V/ns mV/ns
2 3
1. In general, all PCI components must work with any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low times are not violated. For example, the use of spread spectrum techniques to reduce EMI emissions is included in this requirement.
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GL9701 PCI ExpressTM to PCI Bridge
Refer to Section 7.6.4.1 for the spread spectrum requirements for 66 MHz. The clock may only be stopped in a low state. A variance on this specification is allowed for components designed for use on the system board only. These components may operate at any single fixed frequency up to 33 MHz and may enforce a policy of no frequency changes. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 4-7. 3. The minimum RST# slew rate applies only to the rising (deassertion) edge of the reset signal and ensures that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range. RST# waveforms and timing are discussed in Section 4.3.2.
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 8 Package Dimension
D D1 D2 D A A2 A1
96 97
65 64
Internal No.
A
GL9701 AAAAAAAGAA YWWXXXXXXXX
Date Code Lot Code
Green Package
B
Code No.
128 1 32
4X e b
33
4X aaa C A B D c ddd M C A B s D s bbb H A B D
01 0
C ccc C
SEATING PLANE
02 R1 H R2
0.25mm
GAGE PLANE
S
L
03 -
NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. A 1.60 0.063 A1 0.05 0.15 0.002 0.006 1.35 A2 1.40 1.45 0.053 0.055 0.057 D 16.00 BASIC 0.630 BASIC E 16.00 BASIC 0.630 BASIC D1 14.00 BASIC 0.551 BASIC E1 14.00 BASIC 0.551 BASIC D2 12.40 BASIC 0.488 BASIC E2 12.40 BASIC 0.488 BASIC R1 0.08 0.003 R2 0.08 0.20 0.003 0.008 0 3.5 7 0 3.5 7 0 0 01 0 02 11 12 13 11 12 13 03 11 12 13 11 12 13 c 0.09 0.20 0.004 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF S 0.20 0.008 b 0.13 0.16 0.23 0.005 0.006 0.009 e 0.40 BASIC 0.016 BASIC TOLERANCES OF FORM AND POSITION aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.07 0.003
Figure 8.1GL9701 128 Pin LQFP Package
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GL9701 PCI ExpressTM to PCI Bridge
CHAPTER 9 ORDERING INFORMATION
Table 9.1Ordering Information
Part Number GL9701-MXG Package 128-pin LQFP Green Green Package Version XX Status Available
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